1. Field of the Invention
The present invention generally relates to the field of semiconductor memories, particularly to electrically programmable memories and, even more particularly, to non-volatile memories such as, for example, EPROMs, EEPROMs and Flash memories. Specifically, the invention concerns a method of programming a multi-level, electrically programmable non-volatile memory.
2. Description of the Related Art
Electrically programmable, non-volatile semiconductor memories have memory cells formed by MOS transistors, whose threshold voltage can be varied electrically in order to store the desired information.
The number of different values that the threshold voltage of a memory cell may take depends on the number of bits that the memory cell is intended to store. For example, in two-levels memories having memory cells intended to store only one bit each, the threshold voltage of each memory cell can take one of two different values, which are associated with the two opposite binary logic states (“1” and “0”). In multi-level memories, whose memory cells are intended to store more than one bit, the number of different threshold voltage values is equal to 2n, where n identifies the number of bits stored in each memory cell. Multi-level memories are also known in which n bits are stored in k memory cells, with k<n and n/k is not necessarily an integer number; in this case, the number of different values that the memory cell threshold voltage may take is higher than two, but not necessarily equal to a power of two.
Programming a memory cell means bringing the memory cell threshold voltage to the desired value, starting from a memory cell erased condition in which the threshold voltage value is equal to or lower than the lowest of the prescribed values. Typically, in order to increase the memory cell threshold voltage, electrons are injected into a memory cell conductive floating gate of, e.g., polysilicon, or into a memory cell charge-trapping element (typically, a layer of silicon nitride); the charge present in the floating gate or trapped in the charge-trapping element affects the formation of a conductive channel when a gate voltage is applied to a memory cell control gate.
Electrons are for example injected into the floating gate or charge-trapping element by means of the channel hot-electron injection mechanism, which is triggered by applying suitable programming voltages to the memory cell terminals; this mechanism is typically exploited in EPROMs and Flash memories having the so-called NOR architecture. Another mechanism of injecting electrons into the floating gate or charge-trapping element is electron tunnelling; this mechanism is for example exploited in EEPROMs and in EPROMs and Flash memories with the so-called NAND architecture.
The data stored in the memory cell are retrieved by accessing the memory cell in read conditions. Prescribed read voltages are applied to the memory cell terminals, and, e.g., the current sunk by the memory cell is sensed. The higher the memory cell threshold voltage, the lower the current sunk by the memory cell.
The data stored in the memory cell are thus determined by comparing the sensed current to a prescribed reference current or, in the case of a multi-level memory, to a plurality of reference currents.
Multi-level memories, especially of the Flash type, are experiencing an increasing market demand. Features such as high storage density, compactness, ruggedness, low cost, low power consumption make multi-level memories particularly adapted to applications such as silicon storage disks, palmtops, digital still cameras and memory cards. The reason of the success of multi-level memories is that they offer storage densities achievable only by means of two-levels memories of more advanced technological generations, allowing in this way to take full advantage of an already mature technology.
Conventional programming methods of multi-level memories call for programming in parallel a relatively high number of memory cells, so as to increase the programming speed; for example, in four-levels memories, sixty-four memory cells (i.e., 128 data bits) are programmed in parallel, irrespective of the different programmed states that the different memory cells are intended to reach. A sequence of programming pulses is applied to the group of memory cells to be programmed. Each programming pulse provides for applying to the memory cell terminals the proper programming voltages for a prescribed, relatively short time; in particular, the voltage applied to the memory cell control gate is progressively increased at each programming pulse: it has in fact been observed that if the voltage applied to the memory cell control gate is progressively increased at each programming pulse, the memory cell threshold voltage progressively increases following the increase in the control gate voltage.
The lower the control gate voltage increase at each programming pulse, the finer the positioning of the threshold voltage; typically, the control gate voltage undergoes a swing of about 7 V, with an increase of approximately 0.3 V at each programming pulse.
Each programming pulse determines a slight increase in the memory cell threshold voltage. After each programming pulse, a program verify is performed: the memory cells under programming are read to assess whether they have reached the intended programmed state. No more programming pulses are applied to the memory cells that are assessed to have reached the desired programmed state.
The programming operation ends when all the memory cells to be programmed are assessed to have reached the desired programmed state. In the conventional programming method, both the programming current and the programming speed are proportional to the number of memory cells programmed in parallel to each other; in other words, the speed/power ratio is constant.
The Applicant has observed that due to the relatively high degree of parallelism of the program operation, there is a relatively high statistical probability that at least one of the memory cells has to be brought to the programmed state more distant from the erased state, i.e. the programmed state corresponding to the highest threshold voltage level (in a four-levels memory cell, this state is conventionally referred to as the “00” state). This means that, given the small increase of the control gate voltage at each programming pulse, a relatively high number of programming pulses have to be applied for programming these memory cells; by way of example, twenty to twenty-five programming pulses may have to be applied (each one followed by the respective program verify phase). The programming time is typically relatively long and substantially independent from the pattern of data to be programmed.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.